This invention relates to semiconductor memories and more particularly to a semiconductor memory having a data line arrangement of folded data line type suitable for realization of a low noise dynamic memory having a wide operating margin.
The inventors of this invention have studied in various points a semiconductor memory of a so-called folded data line type arrangement wherein as shown in FIG. 1, a plurality of fundamental units having each a pair of data lines and a sense amplifier associated therewith are juxtaposed or arranged in parallel with each other. With this arrangement, the paired data lines are affected by a signal line perpendicular thereto through capacitance coupling between the data line pair and the signal line to cause a coupling noise of common mode which can be cancelled out and low noise can be realized very effectively.
However, as the bit density of the semiconductor memory increases, elements of the memory become finer and finer, giving rise to an increase in various kinds of stray capacitance and especially an increase in capacitance coupling between data line pairs, which leads to increased noise. Accordingly, it is indispensable for realization of a highly integrated semiconductor memory that the folded data line type arrangement be reinforced with a countermeasure against this type of noise. The present inventors have analyzed the noise experimentally and theoretically in detail to find out a noise generating mechanism to be described below which has hitherto been unknown.
The process through which the noise is generated will be described with reference to FIG. 1. In FIG. 1, D1/D1, D2/D2 and D3/D3 designate pairs of data lines, S1, S2 and S3 sense amplifiers for amplifying signal voltages on respective data line pairs, W a word line extending perpendicularly to the data line pair, P a plate electrode for applying a fixed voltage to one end of storage capacitor of a memory cell, and SUB a semiconductor substrate. Further, C.sub.D12 and C.sub.D23 designate coupling capacitance between adjacent data line pairs, CDW coupling capacitance between the data line pair and the word line, CDP coupling capacitance between the data line pair and the plate electrode, and CDS coupling capacitance between the data line pair and the substrate.
The newly found noise generating mechanism teaches that when a difference in signal voltage is caused by, for example, a hit of an alpha-particle between adjacent data line pairs, a difference in operating timing takes place between a sense amplifier associated with a data line pair and another sense amplifier associated with the adjacent data line pair and the noise which is generated through coupling capacitance is amplified to a level being twice or three times as large as that which is conventionally known. For example, when assuming that signal voltages applied to the data line pairs D1/D1 and D3/D3 are larger than those applied to the data line pair D2/D2 in FIG. 1, waveforms as shown in FIG. 2 appear on the data line pairs during the operation of the sense amplifiers associated with the data line pairs. When larger signal voltages on the data line pairs D1/D1 and D3/D3 begin to be amplified at time t.sub.o, signal voltages appearing on the data line pair D2/D2 are too small to permit the gate/source voltage of the MOS transistor constituting the sense amplifier associated with the data line pair D2/D2 exceed a threshold voltage and are not amplified yet. When voltage on the data line D1 or D3 is amplified to a low-level voltage in accordance with read information, voltage on the data line is affected by that amplification through capacitance coupling of the coupling capacitance C.sub.D23 so as to be changed to a low-level voltage more greatly than voltage on the data line D2. Conversely, when voltage on the data line D1 or D3 amplified to the low-level voltage, voltage on the data line D2 is affected by that amplification through capacitance coupling of the coupling capacitance C.sub.D12 so as to be changed to a low-level voltage more greatly than voltage on the data line D2.
Accordingly, during an interval of delay time .tau..sub.d (=t.sub.1- t.sub.0) preceding the initiation of amplification by the sense amplifier associated with the data line pair D2/D2, the voltage on the data line pair D2/D2 affected by the voltage on the adjacent data line pair through capacitance coupling to cause a voltage change which is equivalent to a noise.
In this manner, the newly found noise which depends on the distribution of the read information (data pattern dependent noise) is generated.
In the above example in which amplification proceeds in only one direction, there arises an additional problem that sensitivity of the sense amplifier is degraded and the data pattern dependent noise grows. As shown in FIG. 1, principal capacitance associated with the data line includes capacitance C.sub.DW between the word line and the data line, capacitance C.sub.DP between the plate electrode and the data line and capacitance C.sub.DS between the substrate and the data line. When larger signal voltages on a majority of data line pairs including the data line pairs D1/D1 and D3/D3 are amplified, the half of all of the data lines changes to the low-level voltage and the non-selected word lines W, plate electrode P and substrate SUB are affected by the data lines through capacitance coupling to change to the low-level voltage. This voltage change causes, through capacitance coupling, lower signal voltage on the data line pair D2/D2 to assume a change to a low-level voltage. This further retards the operating timing for the sense amplifier associated with the data line pair D2/D2 and the voltage, still remaining not amplified, decreases greatly. Since the capacitance associated with the data line principally includes C.sub.DW, C.sub.DP and C.sub.DS and the electric impedance of each of the word line, plate electrode and substrate is high, the aforementioned voltage drop is great. As will be seen from the above, when the operating timing for a sense amplifier associated with a particular data line is retarded, the particular data line becomes liable to be affected by other data lines through capacitance coupling and its operating reliability tends to be degraded. Values of the capacitances C.sub.DW, C.sub.DP and C.sub.DS depend on characteristics of semiconductor fabrication process and tend to be slightly different for individual data line pairs and the amount of the aforementioned voltage drop is also slightly different for the individual data line pairs, leading to an operating failure.
A method for eliminating the former noise or the data pattern dependent noise is disclosed in JP-A-62-51096. In this method, a pair of data lines transposed at an odd number of places, that is, data line pair D2/D2 and a pair of data lines transposed at an even number of places, that is, data line pair D1/D1 or D3/D3 are arranged alternately as illustrated in FIG. 3a. There are seen in FIG. 3a memory cells represented by reference numeral 1, word lines W11 to W4N, sense amplifiers S1 to S3, switches Y1 to Y3 for connecting the data lines to common data lines 2 and 3, and a Y decoder 4. This method is called a transposing technique and has already been known as a countermeasure for prevention of interference between a pair of data transmission lines. For example, U.S. Pat. No. 3,305,846 in 1967 describes the transposing technique.
According to this technique, since a pair of data lines transposed at least once, generally, odd times and a pair of data lines transposed at least twice, generally, even times are arranged alternately, changes in voltage caused through capacitance coupling between adjacent data line pairs can be averaged to reduce data pattern dependency.
However, because of the latter problem, that is, the use of the sense amplifier as shown in FIG. 3b in which amplification proceeds in one direction, the newly found amplification of capacitance coupling noise due to delay in operation time of the sense amplifier can not be prevented and degrading the operating margin can not be avoided. Further, it should be noted that no account has conventionally been taken of characteristics of the semiconductor memory. For example, necessity of transposition at least three places prevents high density integration of the memory, a failure to consider data pattern dependent noise due to capacitance coupling in the sense amplifier section leads to a large amount of noise due to the capacitance between lines in the sense amplifier section which occupies several of tens of percent of the capacitance between data lines, and no account is taken of the memory array structure including dummy cells. For these reasons, a practical semiconductor memory having high operating reliability has not been realized yet.